

module exam1( 
input led_clk, 
output led_io
);

reg led_io;
reg [23:0] clkcount;

always @ (posedge led_clk)
begin
    clkcount <= clkcount+1;
    if ( clkcount[23] != 1'b0 ) 
    begin
        led_io <= led_io ^ 1'b1;
    end
end

endmodule

